The invention relates to complementary metal oxide semiconductor (CMOS) devices, and in particular, relates to a low power type of oscillator. Normally, an oscillator is created using a CMOS inverter by coupling a resonant circuit between the output and input terminals. Such oscillators draw very little current and operate best when the applied voltage is equal to the sum of the P-channel and N-channel device threshold voltages. Once the voltage is reduced below this value the circuit performance deteriorates rapidly. Oscillator startup will not occur for supply-voltage values below the sum of device thresholds. While the circuit operates in class B at sum of thresholds, when the supply voltage exceeds the value, switching transients become a problem and the circuit will draw appreciable current in oscillator operation. While this current is low and while CMOS circuitry has gained widespread use in battery-operated devices, it would be desirable to reduce the current drain.
U.S. Pat. No. 4,211,985 shows one approach to current drain reduction. High value resistance elements are coupled in series with the drain electrodes in a CMOS inverter. Each transistor is biased by returning its gate through a high value resistance to its drain. This forces each transistor to operate at its threshold. To operate effectively, this oscillator is coupled to a second CMOS inverter pair which is biased from the same resistors, but has its collectors commonly connected.